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an10911 sd(hc)-memory card and mmc interface conditioning rev. 01 ? 29 april 2010 application note document information info content keywords sd-memory card, multi media card (mmc), electrostatic discharge (esd) protection, electromagn etic interference (emi) filtering, voltage level translator abstract the document gives an overview about different esd protection and emi filter devices optimized for sd-memory card and mmc interfaces. covering the full range from old 1-bit to latest state-of-the-art 4-bit (sd-memory card, sd 2.0) or 8-bit (mmc) high-speed memory card interfaces. further more, solutions including voltage-level translation and also the appropriate power supply for the memory cards are explained.
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 2 of 37 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning revision history rev date description 01 20100429 initial version
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 3 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 1. introduction the sd-memory card and mmc are the most popular memory cards in today?s communication, computer and consumer ap pliances. they are designed to support state-of-the-art security and capacity requi rements demanded by today?s audio and video applications in consumer and communication products. sd-memory cards support content protection , prevention of illegal use of content and security systems based on e.g. iso-7816. th e mmc is available as an embedded version emmc according the jesd84-a43. it offers up to an 8-bit wide interface and can basically be operated in sd-memory card compatible hardware interfaces. while the sd-memory card adds an advanced memory/data storage function to an application, there is a more general se cure digital input output (sdio) card. the sdio card specification is a separately specified interface to different i/o units providing various functions to an sd host, incl uding memory storage that is supposed to be compatible with the sd-memory card specific ation. even if an sd host is not sdio compatible, i.e. just supporting sd-memory cards ? no physical damage or disruption of operation shall occur. a typical sd-memory card communication is based on an advanced 8/9-pin interface (clock, command, 1- or 4-bit data and 2/3 x power/gnd) designed to operate at a maximum operating frequency of 50 mhz. the mmc works with an up to 52 mhz clock but supports in its latest versions up to 8 data bits in a 13-pin interface (clock, command, 1-, 4- or 8-bit data, 3x power/gnd). while the sd-memory card is supposed to contain some esd protection (please refer to chapter 8.1.3. of ref. 1 ? sd specifications, part 1, physical layer specification version 2.00, may 9, 2006 ? ), sd host interfaces require an additional high-level esd protection according the iec61000-4-2 standard in addition to the host-interface integrated esd protection which is typically very weak. further more, strict emi regulations and system requirements as specified in gsm mobile phones strongly request filters that re duce the radiated/conduct ed emi but still comply with the electrical requirements of the interface specification. in addition, the continuing trend of miniatur ization of portable appliances implies that interface devices offering esd protection and emi filtering should also, where possible, integrate biasing circuits/resistors into a single small-sized package. the nxp semiconductors sd-memory card inte rface conditioning devices explained in this document fully support this continuing trend and offer interface conditioning functions such as: ? high-level esd protection according the ie c61000-4-2 standard, often exceeding the highest specified level 4 ? emi filtering, suppressing unwanted radi o frequencies (rf), in combination with sd interface compliant physical signaling ? integrated biasing resistor networks to reduce the component count and to free up additional space on the printed-circuit board (pcb) surface ? a regulated power supply to supply sd-m emory cards directly from e.g. a battery
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 4 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning ? voltage level translation to enable the use of low-voltage host processors to communicate with 2.7 v to 3.6 v compliant sd-memory card devices 2. sd-memory card electrical interface today, most appliances use the (2.7 v to 3.6 v) operating mode. this enables the use of a fixed voltage interface and power supply to reduce cost and comple xity of the control circuitry. all further descriptions are related to this ?high-voltage range? 2.7 v to 3.6 v supply voltage operated interfaces. a list of sd-memory card threshold levels for the high-voltage range is listed in ta b l e 1 . 2.1 bus operation conditions the minimum output level of the driving devi ce and the receiving device input level are specified in ta b l e 1 (taken from ref. 1 ). to decouple the sd-memory card interface specification from the signal-conditioning device (emi filter, esd protection, etc.), an intermediate signal threshold is specified in ta b l e 2 . this ?emi filter, card interface side? leveling is taken as a minimum requirement for an sd-memory card compliant interface conditioning device. as esd protection and emi filter devices shou ld be placed as close as possible to the contacts of the protected interface and in tegrate a major portion of the total bus capacitance c bus , they are expected to be responsible , as any other filter device would be, for the majority of the voltage drop. subsequently, the high-level and the low-level ou tput voltages of the filter or conditioning device can be reduced (refer to v oh , v ol in ta b l e 2 ) compared to the output threshold levels specified in ref. 1 and still exceed the input volta ge level requirements (refer to ta b l e 1 for values specified in ref. 1 ) (see also table note 1 and 2 on page 5 ). a detailed graphical overview of the different th reshold levels at different positions of the signal path is depicted in figure 1 , starting with the driver output on the left side and ending with the receiving side on the right side of the drawing. the three different threshold levels are shown in relation to each other in figure 2 , comparing the sd-memory card output, the nxp signal-conditioning device output and the sd-memory card input threshold levels. table 1. sd-memory card threshold level for high-voltage range values taken from ref. 1 symbol parameter condition min max unit v sd sd-memory card supply voltage 2.7 3.6 v v oh high-level output voltage i oh = ? 100 a; v sd =2.7v 0.75*v sd -v v ol low-level output voltage i ol =100 a; v sd =2.7v - 0.125*v sd v
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 5 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning [1] sd-memory card specification is: v oh minimum is 0.75*v sd and v ih minimum is 0.625*v sd in ref. 1 ; nxp v oh minimum is 0.7*v sd . [2] sd-memory card specification is: v ol maximum is 0.125*v sd and v il maximum is 0.25*v sd in ref. 1 ; nxp v ol minimum is 0.2*v sd . [3] the 20 % to 70 % limits are chosen to cove r also the mmc specification more easily. v ih high-level input voltage 0.625*v sd -v v il low-level input voltage - 0.25*v sd v t pup power up time 0 v v sd 2.7 v - 250 ms table 2. sd-memory card operating conditions symbol parameter min max unit v sd sd-memory card supply voltage 2.7 3.6 v i dd supply current in high-speed mode - 200 ma v oh high-level output voltage [1] [3] 0.7*v sd -v v ol low-level output voltage [2] [3] -0.2*v sd v c l load capacitance - 40 pf c card sd- memory card signal line capacitance - 10 pf c host + bus capacitance of host interface and signal bus - 30 pf r cmd ; r dat external pull-up resistor value (except dat3/cd) to prevent bus floating 10 100 k r dat3 sd-memory card internal pull-up resistor value dat3/cd pin only 10 90 k l ch single line inductance - 16 nh fig 1. threshold voltage levels along the signals path table 1. sd-memory card threshold level for high-voltage range ?continued values taken from ref. 1 symbol parameter condition min max unit v oh = 0.75 * v sd v ol = 0.125 * v sd v sd gnd host output, driving emi-filter sd memory card interface, receiving host output voltage thresholds sd memory card input voltage thresholds v sd gnd v ih = 0.625 * v sd v il = 0.25 * v sd nxp interface conditioning output requirement v oh = 0.75 * v sd v ol = 0.125 * v sd v sd gnd v oh = 0.7 * v sd v ol = 0.2 * v sd v oh = 0.7 * v sd v ol = 0.2 * v sd
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 6 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning all further considerations are based on a ch osen 20 % and 70 % threshold respectively (related to the sd-memory card supply voltage v sd ) as specified in ta b l e 2 , unless otherwise indicated. these relative voltage le vels also simplify an alignment with the mmc specification. 2.2 sd-memory card bus timing conditions the sd-memory card interface has different timing requirements for its default mode and the high-speed mode up to 50 mhz clock frequency. special attention should be pa id to the clock signal rise time and fall time requirements (3 ns maximum). as all nxp devices support the high-speed mode that supersedes the default mode requirements, only these requirements are taken into account here. however, the devices explained in this document support both, the default mode and the high-speed mode. [1] other timing parameters such as hold time, set-up time, high-level and low-level are dependent on the host / sd-memory card interface and not significantly influenced by the nxp inte rface conditioning devices. [2] values refer to v oh , v ol specified for the emi filter output. fig 2. threshold voltage levels, output levels versus input levels v oh = 0.75 * v sd v sd v ol = 0.125 * v sd v oh = 0.7 * v sd v ol = 0.2 * v sd v ih = 0.625 * v sd v il = 0.25 * v sd gnd host output threshold level nxp filter output threshold level sd card input threshold level driver side minimum requirement receiver side minimum requirement receiver side minimum requirement table 3. sd-memory card timing conditions (high-speed mode) [1] symbol parameter condition min max unit f pp operating clock frequency 050mhz t r rise time 20 % to 70 % of v dd [2] -3ns t f fall time 70 % to 20 % of v dd [2] -3ns
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 7 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 2.3 capacitive load at the inte rface conditioning device output in the nxp data sheets of devices such as ip4853cx24/lf, ip4352cx24/lf etc. rise time and fall time requirements are specified similarly to the data shown in ta b l e 4 (taken from the ip4853cx24/lf data sheet). the following abbreviations are used: ? z load : capacitive load representing c pcb2 + c hold + c card in the nxp data sheets ? c pcbx : pcb trace capacitance ? c hold : card holder capacitance ? c bus : total (single) bus channel capacitance excluding the sd-memory card ? c l : total (single) bus channel capacitance including the sd-memory card (for further details, please refer to figure 3 .) in this specification, z load represents c card and a part of c bus . figure 3 depicts the various basic capacitances of the signal path summing up to: please note that a significant portion (nxp assumption 20 % to 30 %) of the sd-memory cards available on the market today, have a card capacitance (c card ) of more than 10 pf. according the sd-memory card specification, the total channel capacitance c l is defined as: assuming that state-of-the-art host interfaces show a capacitance of and the nxp interface-conditioning devices add a capacitance in the range of , a capacitance of is left for the routing on the pcb and the card holder, which can already amount to 3 pf to 5 pf. due to z load representing a lumped capacitance of 20 pf in addition to the filter channel capacitance, it is obvious that the rise time and fall time requirement of 3 ns can be easily fulfilled. table 4. extract from the ip4853cx24/lf data sheet t amb =25 c, v cc = 1.8 v, v bat = 3.5 v, v sd = 2.9 v. high-ref = 70 %*v sd , low-ref = 20 %*v sd symbol parameter test conditions min typ max unit t r , t f rise time, fall time z load =20pf||100k -1.52.5ns t r , t f rise time, fall time z load =40pf||100k -2.73.6ns c bus c pcb1 c ch /2 c ch /2 c pcb2 c hold 30 pf +++ + = c l c bus c card 40 pf + = c host 4 pf c ch 2c ch /2 20 pf = c pcb1 c pcb2 c hold 6 pf ++
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 8 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning a. basic simplified memory card signal channel b. more detailed level c. detailed memory card signal channel show ing the relevant capacitive contributors fig 3. basic signal channel depicted in three different detail levels host interface emi-filter memory card interface c host c bus note: c bus is a lumped representative of the total channel capacitcance of pcb, interface conditioning device and card holder etc . c host c ch/2 sd: c host + c bus = 30 pf mmc: c host + c bus = 18 pf c ch/2 c pcb2 c hold c pcb1 c filter = 20 pf sd memory card: c l = 40 pf multi media card: c l = 30 pf sd: c card = 10 pf mmc: c card 12 pf 18 pf sd: c card = 10 pf mmc: c card 12 pf 18 pf a b c
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 9 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 2.4 sd-memory card detect mechanism to detect an sd-memory card, two different mechanisms can be used. the preferred detection mechan ism uses a mechanical switch in the card holder. the other mechanism is based on the pull-up resistor integrated into the sd-memory card. this resistor is connected to the dat3/cd pin (cd = card detect). a detailed schematic showing both detection mechanisms is depicted in figure 5 . if mmc and sd-memory card shall be used in the same holder, only the mechanical switch-based card detection can be used. in contrast to the sd-memory card specificat ion, the mmc specificat ion does not specify any internal pull-up resistors for an electrical card detection mechanism. additionally, the sd-memory card specificatio n gives clear priority to the mechanical switch detection method. 3. mmc electrical interface advanced appliances optimized for low-power consumption can operate mmc?s at two different supply voltages with the slight disa dvantage of the increased control effort and a selectable supply voltage. a number of mmc threshold levels for the high-voltage range are listed in ta b l e 5 . 3.1 bus operating conditions the minimum output level of the driving devi ce, together with the receiving device input level is specified in ta b l e 5 (taken from ref. 2 ? multi media card system specification version 4.3, jesd84-a43, november 2007 ? ). similar considerations as shown in section 2.2 ? sd-memory card bus timing conditions ? have to be applied for the mmc, too. for high-voltage operation mode, the threshold conditions are identical to the sd-memory card conditions, so that both can be operated if connected to the same physical interface as long as the electrical card detection mechanism is not used. table 5. mmc threshold levels (values taken from ref. 2 ) symbol parameter condition min max unit v mmc mmc supply voltage high-voltage range 2.7 3.6 v low-voltage range [1] 1.7 1.95 v push-pull mode bus signal level for high-voltage mmc v oh high-level output voltage i oh = ? 100 a; v mmcmin 0.75*v mmc -v v ol low-level output voltage i ol =100 a; v mmcmin -0.125*v mmc v v ih high-level input voltage 0.625*v mmc v mmc +0.3 v v il low-level input voltage v ss ? 0.3 0.25*v mmc v
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 10 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning [1] low-voltage levels are part of the dual voltage r ange card specification including also the high-voltage range. the voltage range from 1.95 v to 2.7 v is undefined. compared to the sd-memory card, the mmc bus is limited to a maximum of only 30 pf (sd-memory card is 40 pf maximum). the emmc contains pull-up resistors at the pins data0 to data7 to prevent floating of unconnected data lines. all other mmcs do no t contain any pull-up resistors to prevent bus floating. two basic differences are the minimum resistor value of r cmd which is less than half the specified minimum of the sd-memory card specification, and the data0 to data7 pull-up resistor values, starting at 50 k instead of 10 k in the sd-memory card specification (see table 2 for details). push-pull mode bus signal level for the du al voltage mmc in 1.70 v to 1.95 v mode, for high-voltage specified above for high-voltage mmc v oh high-level output voltage i oh = ? 100 a; v mmcmin v mmc ? 0.2 - v v ol low-level output voltage i ol =100 a; v mmcmin -0.2v v ih high-level input voltage 0.7*v mmc v mmc +0.3 v v il low-level input voltage v ss ? 0.3 0.3*v mmc v table 6. mmc operating conditions symbol parameter min max unit c l total bus capacitance for each signal line - 30 pf c card single card signal line capacitance c micro -12pf c mobile -18pf c bga -12pf r cmd cmd pull-up resistor value 4.7 100 k r dat7-0 external data7 to data0 pull-up resistor value (except emmc) 50 100 k r intdat emmc internal data7 to data0 pull-up resistor value 50 150 k l ch maximum signal line capacitance - 16 nh table 5. mmc threshold levels ?continued (values taken from ref. 2 ) symbol parameter condition min max unit
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 11 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 3.2 bus timing conditions the mmc interface has different timing requirements for its default mode and the high-speed mode running up to 52 mhz. special attention should be paid to the clock signal rise time/fall time requirement (3 ns ma ximum) which is similar to the high-voltage range cards and the sd-memory card timing conditions (see ta b l e 3 ). also, a reduced clock speed of up to 26 mhz can be used with these cards to save power in appliances that do not require high data rates. as all nxp devices support the high-speed mode that supersedes the default-mode requirements, only these requirements are taken into account here. however, the devices explained in this document support both, the default-mode and the high-speed mode. [1] other timing parameters such as hold time, set-up time, high-time and low-time are dependent on the host / mmc interface and are not significantly in fluenced by the nxp interf ace conditioning devices. [2] please refer to ref. 2 , chapter 12.7.1 for further details. 3.3 capacitive load at the inte rface conditioning device output please refer to section 2.3 for a detailed overview and calculation. the drawings depicted in figure 3 show that it is difficult to build an mmc specification-compliant bus system that includes high-level esd protection and emi filtering. nevertheless, most implementa tions used are basically related to the sd-memory card application and use only slightly higher total channel capacitances, reaching the sd specificat ion for the value of c host + c bus . table 7. mmc timing conditions (high-speed mode) [1] symbol parameter min max unit f pp operating clock frequency 0 (26)/52 mhz t rise high-speed mode clock rise time [2] -3ns t fall high-speed mode clock fall time - 3 ns
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 12 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 4. sd-memory card and mmc interface comparison a short summary of the main electrical in terface parameters of the sd-memory card versus the mmc are listed in the following table: 5. passive esd protection and emi filter devices nxp semiconductors offers a wide range of dev ices for the interface conditioning of the sd-memory card and/or mmc interface. the product range covers basic emi filters and esd protection devices (ip4252cz12-6 or ip4252cz16-8) up to a fully integrated interface device containing voltage translat ors, ldo, emi filtering, high-level esd protection, and all required biasing/pull-up/p ull-down resistors integrated into a single monolithic ip4853cx24/lf. besides the sd-memory card or mmc interface mode, these devices can be used for e.g. serial peripheral interface (spi)-based interf ace operation modes, too. in this case, 4-channel devices can be used although this is not the preferred method of data exchange with sd-memory cards due to the lower speed and only single bit access. a basic overview is given in ta b l e 9 and a detailed description is given in the next chapters. passive filter devices are available in lead less plastic packages (dfn) and wafer level chip size packages (wlcsp) while the solu tions incorporating active devices are available in wlcsp only. table 8. sd-memory card vs. mmc main electrical parameters symbol parameter sd-memory card mmc unit v sd/mmc memory card supply voltage high-voltage range 2.7 - 3.6 2.7 - 3.6 v low-voltage range - 1.7 - 1.95 v f pp operating clock frequency 50 (max) 52 (max) mhz t rise/fall high-speed mode clock rise time/fall time 3 (max) 3 (max) ns c l total bus capacitance for each signal line 40 (max) 30 (max) pf c card single card signal line capacitance 10 (max) -pf c micro ; mmc only - 12 (max) pf c mobile ; mmc only - 18 (max) pf c bga ; mmc only - 12 (max) pf r cmd cmd pull-up resistor value 10 - 100 4.7 - 100 k r dat7(3)-0 external data7(3) - data0 pull-up resistor value mmc (sd) to prevent bus floating (except emmc) 10 - 100 50 - 100 k r intdat3 emmc internal data7- data0 pull-up resistor value (emmc only) - 50 - 150 k dat3/cd (sd) 10 - 90 - k l ch maximum signal line capacitance 16 (max) 16 (max) nh
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 13 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning even though the mmc and sd-memory card specifications state exact minimum and maximum values for the various internal and external pull-up and pull-down resistors, a majority of implemented interfaces in available appliances do not follow these recommendations. especially the minimum cmd signal pull-up resistor value is often undercut to guarantee a sufficiently short rise time in an open-drain communication mode. (or: this is especially true for the minimum cmd signal pull-up resist or value, which is often undercut to guarantee a sufficiently short rise time in an open-drain communication mode.) the minimum values of the external pull-up resistor values of the mmc specification are also sometimes replaced by values from the sd-memory card specification range. therefore, most nxp integrated discretes devices can be used in both interface applications, mmcs and sd-memory cards, even though the data sheet is referring to just one interface type! today's state-of-the-art memory cards will typically support in terfaces which are slightly out of the related general interface specification. table 9. sd-memory card and mmc interface devices overview product name device type additional features number of filter channels package type and size memory card interface esd protection and emi filter devices with integrated biasing (pull-up-/pull-down) resistors, esd protection level of > 15 kv contact, far exceeding th e iec61000-4-2, level 4 (8 kv contact, 15 kv air) ip4051cx11/lf passive, esd protection and emi filter 4 csp, 0.5 mm pitch [1.96 2.54 mm 2] ip4052cx20/lf passive, esd protection and emi filter 6 csp, 0.5 mm pitch [1.96 2.54 mm 2] ip4060cx16/lf passive, esd protection and emi filter 6 csp, 0.5 mm pitch [2.01 2.01 mm 2] ip4350cx24/lf passive, esd protection and emi filter inclusive wp and cd 6 (+5) [1] csp, 0.4 mm pitch [2.01 2.02 mm 2] ip4352cx24/lf passive, esd protection and emi filter inclusive wp and cd 6 (+5) [1] csp, 0.4 mm pitch [2.01 2.02 mm 2] memory card interface esd protection and emi filter d evices, esd protection level according iec61000-4-2, level 4 (8 kv contact, 15 kv air discharge) ip4252cz8-4 passive, esd protection and emi filter 4 dfn, 0.4 mm pitch [1.35 1.7 mm 2] ip4252cz12-6 passive, esd protection and emi filter 6 dfn, 0.4 mm pitch [1.35 2.5 mm 2] ip4252cz16-8 passive, esd protection and emi filter 8 dfn, 0.4 mm pitch [1.35 3.3 mm 2]
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 14 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning [1] numbers in brackets represent additional channels such as pu ll-up and pull-down channels, write protect and card detect that are not required for the basic data communication. 5.1 esd protection emi filter devi ces in plastic package ip4252cz8-4, ip4252cz12-6, ip4252cz16-8 for memory card interfaces only requiring esd protection and/or emi filtering, devices such as ip4252cz8-4 (4-channel) ip4252cz12-6 (6-channel) or ip4252cz16-8 (8-channel) are the devices of choice. they all contain an rc-based pi-filter (als o called capacitor-resistor-capacitor (crc) filter) consisting of two diodes, acting also as filter capacitors, and a serial channel resistor connected between the cathodes of the diodes. a schematic of a single f ilter channel is shown in figure 4 (left side), while the right side of figure 4 depicts the package footprint of the df n plastic package (0.4 mm contact pitch). the maximum package height is 0.5 mm. the most important technical parameters are listed in ta b l e 1 0 . bidirectional memory card interface voltage tran slator device, ic leve l esd protection according iec 61340-3-1, hbm, 2 kv ip4852cx25/lf active, 1.8 v ? 2.9 v voltage translator voltage translators 6 csp, 0.4 mm pitch [2.01 2.01 mm 2] ldo, voltage translators, esd protection and emi filter and biasing resistors included wp and cd, integrated esd protection level according iec61000-4-2, level 4 ip4853cx24/lf active, 1.8 v ? 2.9 v voltage translator ldo 6 (+3) [1] csp, 0.4 mm pitch [2.01 2.01 mm 2] table 9. sd-memory card and mmc interface devices overview ?continued product name device type additional features number of filter channels package type and size a. single channel schematic b. ip4252cz4-8, ip4252cz12-6 and ip4252cz16-8 package (top to bottom) fig 4. ip4252: schematic view and package photograph 001aaf980 r s(ch) 9, 10, 11, 12, 13, 14, 15, 16 1, 2, 3, 4, 5, 6, 7, 8 gnd c ch 2 c ch 2
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 15 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning due to the integrated symmetric al pi-filter structure, also often referred to as crc structure, all nxp semiconductors ip425x devices offer a direction-independent and symmetrical esd protection as well as a dire ction-independent and symmetrical emi filter performance. the integrated pi-filter structures result in a very low esd clamping voltage compared to single diode esd protection implementations and/or devices. 5.1.1 application details of ip4252cz12-6 and ip4252cz16-8 the schematic drawing depicted in figure 5 shows a typical application of ip4252cz12-6 and/or ip4252cz16-8 in an sd-memory card interface including both options for card detection. the grey-colored components are op tional and depend on the exact details of the interface implementation. especially with re spect to the card detect mechanism, either using a mechanical switch in the ca rd holder (preferred according ref. 1 ) or the use of the integrated pull-up resistor at pin dat3/cd in combination with selectable pull-down / pull-up resistors, the exact resistor values hav e to be aligned with all details described in ref. 1 . this schematic does not include details conc erning card-supply and typical power-supply decoupling capacitors. for the basic sd-memory card operation an ip4252cz12-6 and 4 pull-up resistors (10 k to 100 k ) are sufficient for the digital data transmission from and to the sd-memory card. mmcs require higher pull-up resistor values starting at 50 k . the card-detection mechanism has to be implem ented using a cd channel as depicted in figure 6 , based on a mechanical card-detection switch in case sd and mmc are used with the same interface. table 10. ip4252 parameters symbol parameter conditions min typ max unit v cc supply voltage ? 0.5 - +5.6 v v esd electrostatic discharge voltage all pins to gnd iec 61000-4-2, level 4 contact discharge ? 8- +8kv air discharge ? 15 - +15 kv r s(ch) channel series resistance 32 40 48 c ch channel capacitance v dc = 0 v, f = 100 khz - 18 - pf v dc = 2.5 v, f = 100 khz - 12 - pf 2 ? c ch 2 ---------- - =
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 16 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning the implementation of a write-protect (wp) cont act is only possible in applications which are supporting standard size sd-memory cards. smaller form-factor versions such as mini-sd or micro-sd do not support this feature. in case the mechanical slider mechanism of the standard size sd-memory card is used, a pull-up resistor is connected to the host supply and a mechanical contact to gnd. this contact is open until a wp slider is closing it. (mechanical adaptors converting a micro or mini sd-memory card into a standard sd-card size do typically not support this feature). fig 5. application schematic diagram of ip4252cz12- 6 and ip4252cz16-8 in a sd-memory card interface cd dat3/cd-pull-up 10 k 100 k dat3/cd-pull-down > 270 k , exact value depends on required logic levels v cc (v sd ) dat1 dat0 clk cmd dat3/cd dat2 cd wp pull-up resistors 10 k 100 k dat1 dat0 gnd clk v cc (v sd ) cmd dat3/cd dat2 optional : 2 -additional channels of ip 4252 cz16 -8 ip 4252 cz12 -6 (ip 4252 cz16 -8) sd memory card to host interface optional electrical card detect optional : card detect switch 10 k 90 k set_clr_card_detect (acmd42) wp optional : w rite protect switch
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 17 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning in case a mechanical card-detection switch is prohibited e.g. due to size constraints for the card holder, an electrical card-detection can be used as an alternative but only for an sd-memory card interface. after power-up, da t3/cd is connected to a 50 k (nominal value, specified range is 10 k to 90 k ) pull-up resistor inside the card. in case dat3/cd is connected to a high-ohmic pull-down resistor (> 270 k to fulfill the logic vo ltage level requirements 1 ), the connected host can detect a logic level change from low to high level. the card internal pull-up resistor should be disconnected during regular data transmission with a set_clr_card_detect (acmd42) command. the basic schematic diagram for th is implementation is shown in figure 7 . fig 6. application schematic diagram of ip4252c z16-8 using a mechanical card detect switch cd v cc (v sd ) dat1 dat0 clk cmd dat3/cd dat2 cd wp pull -up resistors 10 k 100 k dat1 dat0 gnd clk v cc (v sd ) cmd dat3/cd dat2 ip4252 cz16 -8 sd memory card to host interface wp 1. the exact value depends on the logic level requirements.
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 18 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning for the latest 8-bit mmc interface, 10 channels have to be esd-protected and emi-filtered. a combination of ip4252cz8-4 (4-channel) and ip4252cz12-6 (6-channel) is best-matching filter combination to cover the full interface ( figure 8 ). fig 7. application schematic diagram of ip425 2cz12-6 using electrical card detection 50 k pull-up dat3/cd-pull-down > 270 k , exact value depends on required logic levels v cc (v sd ) dat1 dat0 clk cmd dat3/cd dat2 pull-up resistors 10 k 100 k dat1 dat0 gnd clk vcc(v sd ) cmd dat3/cd dat2 ip 4252 cz12 -6 sd memory card host interface optional electrical card detect set_clr_card_detect (acmd42) fig 8. application schematic diagram of ip4252c z12-6 and ip4252cz8-4 in a 8-bit mmc interface dat0 vss 2 cmd v cc (v mmc ) clk vss 1 dat3 dat1 dat7 dat4 dat5 dat6 dat2 c1 c10 c9 c8 c7 c6 c5 c4 c3 c2 c11 c12 c13 e.g. rsmmc dat1 dat0 dat7 dat6 clk dat5 pull-up resistors 50 k 100 k ip4252 cz12 -6 host interface ip4252 cz8-4 v cc (v mmc ) cmd dat4 dat3 dat2 cmd pull-up resistor see text
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 19 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 5.2 esd protection emi filter devices csp ip4051cx11/lf both devices contain the exact same circui try consisting of four esd-protected and emi-filtered channels, two of which contain pull-up resistors (see figure 9 ). the devices are optimized for the non-high-speed mmc cards but can also be used for the sd-memory card spi mode. the most important parameters are listed below in ta b l e 11 . [1] v cc is the memory card supply voltage, also named v sd or v mmc in this document. [2] device withstands more than 1000 discharges of 15 kv contact discharge according the iec 61000-4-2 model, far exceeding the specified level 4. due to the typical channel capacitance of 25 pf, these devices are not recommended for high-speed compliant memory cards and clock speeds higher than 25 mhz. table 11. ip4051cx11/lf parameters symbol parameter conditions min typ max unit v cc supply voltage [1] ? 0.5 - +5.0 v v esd electrostatic discharge voltage all pins to ground iec 61000-4-2, level 4 contact discharge [2] ? 8( ? 15) - +8(+15) kv air discharge ? 15 - +15 kv r s(ch) channel series resistance 44.65 47 49.35 c ch channel capacitance v dc =0v; f=100khz -25-pf fig 9. ip4051cx11/lf schematic view brb033 47 a3 a2 56 k b2 13 k c2 47 b3 b1 47 c3 c1 47 d3 d1 d2
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 20 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 5.2.1 application information of ip4051cx11/lf in an spi mode sd-memory card interface in case a full 4-bit/8-bit memory card interface implementation on the host side is not required or not possible (e.g. too high design-in effort), sd-memory cards/mmc offer an spi mode interface function. this interface type requires only four interface lines and uses a single-bit physical data transmission with a maximum of 25 mhz clock frequency. please note that the spi mode is no lo nger supported according jesd84-a43, mmc version 4.3 specification. for details, plea se refer to chapter 9, 'spi mode' of ref. 2 . a basic schematic diagram is depicted in figure 10 . resistor 'do-pu' should be connected to v cc in order to avoid bus floating while no card is present. during power-up, cs (dat3/cd) should be pulled high using resistor 'cs-pu' during the first 74 clock cycles and pulled low via the host interface drivers while the card is receiving a reset command (cmd0). this will in itiate the spi interface mode. all unused sd-memory card pins (dat1 and dat3) should be pulled high using additional resistors which are not shown here. 5.3 mmc esd protection and em i filter device ip4060cx16/lf the ip4060cx16/lf is a 6-channel mmc devi ce with 5 additionally integrated pull-up resistors in a tiny 0.5 mm ball pitch csp. the only channel without a pull-up resistor is the clock channel (see schematic diagram in figure 11 , pin b4 to pin a1). due to the pull-up re sistor implementation, the electrical card detection method cannot be used. detection using a mechanical switch is mandatory. the maximum filter channel capacitance is 20 pf which makes the device suitable to work in high clock speed applications, too. fig 10. ip4051cx11/lf sd-memory card spi mode interface schematic diagram 50k pull-up do sclk cs di dat1 dat0 gnd clk vcc(v sd ) cmd dat3/cd dat2 ip4051cx11 sd memory card to spi host interface d2 47r d1 47r 47r c1 b1 a2 b3 c3 d3 47r a3 b2 c2 56k 13k do-pu cs-pu do sclk cs di
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 21 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning [1] v cc is the memory card supply voltage, also named v sd or v mmc in this document. [2] device withstands more than 1000 discharges of 15 kv contact discharge according the iec 61000-4-2 model, far exceeding the specified level 4. table 12. ip4060cx16/lf parameters symbol parameter conditions min typ max unit v cc voltage range [1] ? 0.5 - +5.5 v v esd electrostatic discharge voltage all pins to ground iec 61000-4-2, level 4 contact discharge [2] ? 8( ? 15) - +8(+15) kv air discharge ? 15 - +15 kv r s(ch) channel series resistance 40 50 60 r dat data channel pull-up resistor value 52.5 75 97.5 k r cmd cmd channel pull-up resistor value 4.9 7 9.1 k c ch channel capacitance v dc =0v; f = 100khz -1820pf fig 11. schematic view for ip4060cx16/lf 50r d1 50r 50r c1 b1 b2 c3 d4 d3 50r c4 a1 a2 50r b4 50r a4 a3 75k 75k 75k 75k 7k d2 c2 b3
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 22 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 5.3.1 mmc interfacing using ip4060cx16/lf the ip4060cx16/lf contains esd protection, emi filtering and provides pull-up resistors according to the mmc specification for a 4-bi t interface implementation. even though the cmd line pull-up resistor val ue is lower than the 10 k recommended in the sd-memory card specification, the ip4060cx16/lf is of ten used in conjunction with this interface. a typical application is depicted in the following schematic: 5.4 memory card interface using ip4052cx20/lf another product suitable for the memory card interface is the ip4052cx20/lf. this esd protection and emi filter device contains 6 channels for cmd, clk and 4 data channels plus 2 spare resistors in order to e.g. bias a card detection switch. compared to other devices, the ip4052cx20/lf contains pull-up resistors for the 4 data channels and the cmd channel. in addition, it also contains a relatively low-ohmic pull-up resistor connected to the cmd channel. the maximum filter channel capacitance is 20 pf which makes the device suitable for high clock-speed applications as well. electrical card detection for the sd-memory card is not supported. the most important electrical parameters are listed in ta b l e 1 3 . fig 12. mmc interface schematic diagram for ip4060cx16/lf dat0 vss2 cmd v cc (v mmc ) clk vss1 dat3 dat1 dat7 dat4 dat5 dat6 dat2 c1 c10 c9 c8 c7 c6 c5 c4 c3 c2 c11 c12 c13 50r d1 50r 50r c1 b1 b2 c3 d4 d3 50r c4 a1 a2 50r b4 50r a4 a3 75k 75k 75k 75k 7k d2 c2 b3 vss v cc (v mmc ) t o h o s t i n t e r f a c e e.g. rsmmc
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 23 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning [1] v cc is the memory card supply voltage, also named v sd or v mmc in this document. [2] pins a1, b2, c1, d1, e1, a3, e3 and c3 to ground. [3] device withstands > 1000 discharges of 15 kv contact discharge accordi ng the iec 61000-4-2 model, far exceeding the specified level 4. 5.4.1 sd-memory card interfacing using ip4052cx20/lf the low-ohmic cmd pull-up resistor connected to pin d3 is optional. this pin can be connected e.g. to a gpio pin and set to ?high? for the initial open-drain sequence at the cmd card pin. after this initial stage, the gpio pin can be set to 3-state, so that cmd and the 4 data pins face the sa me pull-up resistor values. the cd switch bias resistors r7 and r8 c an be interconnected in various ways to generate different total resistor values. the circuitry shown in figure 13 serves as a reference. table 13. ip4052cx20/lf parameters symbol parameter conditions min typ max unit v cc supply voltage [1] ? 0.5 - +5.5 v v esd electrostatic discharge voltage iec 61000-4-2, level 4 [2] contact discharge [3] ? 8( ? 15) - +8(+15) kv air discharge ? 15 - +15 kv r 1-6 channel series resistor value 30 40 50 r 7, 8 cd biasing resistor value 37 50 63 k r 10-14 data and cmd pull-up resistor value 18 25 32 k r 15 additional low-ohmic cmd pull-up 0.72 1.0 1.28 k c ch channel capacitance v dc =0v; f = 100khz -1824pf v dc =2.5v; f = 100khz -1520pf
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 24 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning fig 13. ip4052cx20/lf in a typical sd-memory card interface application d1 d4 r3 r12 b1 b4 r2 r11 e1 e2 r5 r14 e3 e4 r4 r13 a1 a4 r1 r10 c3 r15 d3 c1 c4 r6 r8 r7 b3 a2 a3 b2 c2 d2 dat1 dat0 gnd clk v cc (v sd ) cmd dat3/ cd dat2 v cc (v sd ) cd v cc (v sd ) n.c. additional cmd pull-up ip4052cx20/lf gnd t o h o s t p r o c e s s o r i n t e r f a c e
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 25 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 5.5 very highly integrated memory card interface devices ip4352cx24/lf and ip4350cx24/lf the ip4350cx24/lf and the ip4352cx24/lf are products demonstrating the highest level of integration, consisting of esd prot ection, emi filter, and biasing resistors in a passive device. as the package is a 0.4 mm pitch csp type, the total device size is approximately 2 2mm 2 . both devices, ip4352cx24/lf and ip4350cx24/lf fully support high-speed memory card interfaces working with clock speeds up 52 mhz. a special diode structure using a rail-to-rail (also known as ?crow-bar?) diode concept on the high-level esd protection side in combinat ion with the single diodes on the low-level esd protection side guarantee a balanced distribution of the channel capacitance. this leads to symmetrical emi filter performanc e which is independent from the read/write direction. both, the ip4352cx24/lf and the ip4350cx24/lf support electrical card detection of an sd-memory card using the pins dat3_pd and r21 connected to gnd. a detailed schematic showing the driver and control circuitr y required to use electrical card detection is depicted in figure 15 . electrical card detect is available as long as the ?control? inverter is low and 'driver_pu' is 3-stated, so r21 is acting as a pull-down to gnd. if normal operation is needed, the ?control? inve rter has to drive a high signal to enable the 'driver_pu' buffer, drive a high signal at r11 and also to drive r21 to a high level to avoid any unnecessary quiescent current. be aware that the maximum voltage at the pin to the host interface may exceed the host supply voltage as it is derived from: . in this case a voltage tolerant input has to be selected. if electrical card detection is not required, dat3_pu (r11) should be connected to v sd instead. please note, that the cmd line is connected to the pull-up resistor r15 which is typically 15 k , so that ip4350cx24/lf can also be used in combination with an mmc. the mmc can be initialized using a 400 khz open-drain mode. the channels for the mechanical ?write pr otect? wp, the 'card detect' cd, and the combined wp+cd require an additional pull-up resistor which is not integrated. often pull-up resistors integrated into the gpios of t he host processor are used for this as they can be switched off after detection. the basic difference between the ip4352cx24/lf and the ip4350cx24/lf is the channel series resistance, the cmd pull-up resistor value (r15) and the line capacitance. for details, refer to ta b l e 1 4 . the lower cmd pull-up resistor value and lower total line capacitance value make the ip4350cx24/lf an excellent match for mmc interfaces in case a compliance with the latest standard specif ication is mandatory. three additional channels support any config uration of card-detect and write-protect switches for the various memory card holders. the most important electrical parameters are listed in ta b l e 1 4 . v sd ? r 11 r 11 r dat3 /cd_pu + () ? ()
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 26 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning [1] v cc is the memory card supply voltage, also named v sd or v mmc in this document. [2] device withstands > 1000 discharges of 15 kv contact discharge accordi ng the iec 61000-4-2 model, far exceeding the specified level 4. table 14. ip4350cx24/lf and ip4352cx24/lf parameters symbol parameter conditions min typ max unit v sd supply voltage [1] ? 0.5 - +5.0 v v esd electrostatic discharge voltage sdxxx pins to gnd iec 61000-4-2, level 4 contact discharge [2] ? 8( ? 15) - +8(+15) kv air discharge ? 15 - +15 kv r 1-9 channel series resistance ip4350cx24/lf 12 15 18 ip4352cx24/lf 32 40 48 r 11-14 data pull-up resistor value 35 50 65 k r 15 cmd pull-up resistor value ip4350cx24/lf 3.29 4.7 6.11 k ip4352cx24/lf 10.5 15 19.5 k r 21 dat3/cd pull-down resistor 329 470 611 k c ch channel capacitance v dc =0v; f = 100khz ip4350cx24/lf, data, cmd -8.8-pf ip4350cx24/lf, clk -7.8-pf ip4352cx24/lf, data, clk, cmd --20pf
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 27 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning fig 14. ip4352cx24/lf and ip4350cx24/lf connected to a sd-memory card using mechanical card detect fig 15. ip4352cx24/lf and ip4350cx24/lf connecte d to a sd-memory card using electrical card detect
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 28 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 5.6 active memory card voltage translator circuit ip4852cx25/lf the ip4852cx25/lf is a voltage translator op timized to be used in conjunction with a 1.8 v operating host interface and an sd-memory card or a high-voltage range mmc. the device is high-speed compliant, containing a clk channel with an additional feedback channel and 5 bidire ctional voltage translators. the device size is approximately 2 2mm 2 ! these voltage translators are clustered in thre e groups, so that e.g. a single-bit interface operation can be conducted without any energy consumption from switching the data1-3 translators. the host interface (left side of the schematic) voltage range is 1.62 v to 1.9 v. the sd-memory card interface side (right side of the schematic) is 2.5 v to 3.5 v (see also ta b l e 1 5 ). a schematic showing the internal circuitr y of the ip4852cx25/lf is depicted in figure 16 . the ip4852cx25/lf is an excellent ma tch for e.g. the ip4352cx24/lf or ip4350cx24/lf, the ip4060cx16/lf, and the ip4052cx20/lf, but is also suitable to work with other devices listed in this document in order to implement a level shifting function in combination with esd protection, emi filtering, and biasing for memory card interfaces using the smallest possible footprint.
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 29 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning the timing data listed in ta b l e 1 6 show that the ip4852cx25/lf can easily cope with a 40 pf load, even under worst-case conditions. please note that the parameter values under condition t amb =+75 c are valid for a memory card supply level of 2.5 v only. this supply level is below the minimum requirement of 2.7 v for both, th e sd-card and mmc specification. the used high and low limits of 70 % and 20 % are much harder to be fulfilled than those of the original sd-memory card specification. for details, refer to ta b l e 1 . fig 16. ip4852cx25/lf schematic diagram table 15. ip4852cx25/lf electrical parameters symbol parameter conditions min typ max unit v sd sd-card interface side supply voltage 2.5 2.9 3.5 v v cc host interface side supply voltage 1.62 1.8 1.9 v v esd electrostatic discharge voltage iec 61340-3-1, hmb 2 - - kv enb enb data3_sd enb enb data2_sd data1_h data3_h data2_h enb enb data1_sd data0_h die_1_3 gnd v sd v cc en dir_0 enb enb data0_sd cmd_h dir_cmd clk_fb clk_in enb enb cmd_sd clk_sd
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 30 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning table 16. processor side to memory card side timing with high-ref = 0.7*v o , low-ref = 0.2*v o symbol parameter conditions min typ max unit t amb =25 c; v cc(host side) =1.8v; v sd(sd side) =2.9v; high-ref = 70 % * v o (v sd ); low-ref = 20 % * v o (v sd ) t r , t f rise time, fall time z load = 25 pf || 100 k -0.71.8ns z load = 40 pf || 100 k -1.32.6ns t amb = ? 30 c; v cc(host side) =1.9v; v sd(sd side) =3.5v; high-ref = 70 % * v o (v sd ); low-ref = 20 % * v o (v sd ) t r , t f rise time, fall time z load = 25 pf || 100 k -0.61.4ns z load = 40 pf || 100 k -12.2ns t amb =+75 c; v cc(host side) =1.62v; v sd(sd side) =2.5v; high-ref = 70 % * v o (v sd ); low-ref = 20 % * v o (v sd ) t r , t f rise time, fall time z load = 25 pf || 100 k -0.82.7ns z load = 40 pf || 100 k -1.52.9ns
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 31 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 5.7 active memory card vo ltage translator, power supply, esd protection and emi filter device ip4853cx24/lf the highest integration level among the various memory card interface products is offered by the ip4853cx24/lf. this device integrates the level-shifting functionality of the ip4852cx25/lf and the emi filter/esd protection of ip4350cx24/lf with an additional power supply unit (ldo) in a 2 2mm 2 device. the ip4853cx24/lf voltage translator part is optimized to be used in conjunction with a 1.8 v operating host interface and an sd-memory card or a high-voltage range mmc. it is high-speed compliant, contains a clk channel with an additional feedback channel and 5 bidirectional voltage translators plus 2 ad ditional pull-up resistors to bias wp and cd switches. additionally, the memory card interface pins contain high-level esd protection diodes (iec 61000-4-2, level 4, 8 kv contact), and also emi filters to avoid any significant radiation from this interface. another feature is the integrated ldo that ca n be connected directly to e.g. a mobile phone battery to generate a supply voltage of 2.9 v for a connected memory card. the integrated voltage translators are clustered into three groups (as in ip4852cx25/lf), so that e.g. a single-bit interface opera tion can be conducted without any energy consumed by switching the data1-3 translators. the host interface (left side of the schematic) voltage range is 1.62 v to 1.9 v the memory card interface is connected to the ldo out put side (right side of the schematic, pin v sd ) and typically supplies 2.9 v (see also ta b l e 1 5 ). a schematic showing the internal circuitr y of the ip4853cx24/lf is depicted in figure 17 .
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 32 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning fig 17. ip4853cx24/lf schematic diagram 001aah980 cd voltage regulator v bat clk_in vsd clk_sd clk_fb dir_cmd cmd_h r13 r14 r7 r12 r11 r10 r1 r2 dir_0 data0_h cmd_sd data0_sd r3 dir_1_3 data1_h r4 data2_h data3_h v cc enable d3 c2 b3 b1 a1 e1 e3 d1 a3 e4 b5 a5 e5 d5 d4 c5 b4 a4 c1 e2 a2 d2 c3, c4 data1_sd data2_sd host side sd card side data3_sd r5 r6 wp r15 gnd ip4853cx24
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 33 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning some timing data are listed in table 18 . as this device will be located close to the memory card ho lder and no major additional capacitance will be added to the driving out put of the ip4853cx24 /lf (emi filter and esd protection are already integrated), the high and the low limits are intentionally set to 70 % and 20 % to include some safety margin. table 17. ip4853cx24/lf recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage - 1.62 2.1 v v bat battery supply voltage -2.75.0v v i input voltage host side - 0 2.1 v sd-card side; v bat 3.2 v -02.9v v o output voltage host side; active mode (enable = ?1?) -0v cc v sd-card side; active mode (enable = ?1?) -0v o(reg) v t amb ambient temperature - ? 30 +85 c t/ v time difference over voltage change 0.2v cc v i 0.7v cc - - 2 ns/v table 18. processor side to memory ca rd side timing with high-ref = 0.7v o , low-ref = 0.2v o symbol parameter conditions min typ max unit high-ref = 0.7v o and low-ref = 0.2v o ; v bat =3.5v; vsd=v o(reg) =2.9v t t transition time t amb =25 c; v cc =1.8v z load = 20 pf || 100 k -1.52.5ns z load = 40 pf || 100 k -2.73.6ns t amb = ? 30 c; v cc =1.9v z load = 20 pf || 100 k -1.52.5ns z load = 40 pf || 100 k -2.73.6ns t amb =+70 c; v cc =1.62v z load = 20 pf || 100 k -1.82.8ns z load = 40 pf || 100 k -2.93.8ns
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 34 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 6. conclusion nxp semiconductors offers a comprehensive portfolio of sd-memory card and mmc compatible interface conditioning and protection devices. this includes emi filtering, system level esd protection and biasing devices as well as level translators including also the memory card supply ldo. as shown before, the devices are optimized for compliance with their respective memory card interface in terms of channel capacitanc e, serial resistance and biasing resistor values. the passive devices explained in this docume nt protect from destruction from system level esd and also prevent disturbance of e.g. wireless interfaces from the harmonics of the digital memory interfaces while the integr ated biasing resistors contribute to gain the maximum space savings compared to discrete solutions. furthermore, the active devices support level translations, esd protection, emi filtering and power supply via an ldo (ip4853cx24 and ip4852cx25) to allow customers the integration of sd-memory cards in 1.8 v level operating systems. all devices presented support a simple pcb layout, reduce the risk of emi due to complex layout of scattered discrete components and allow to minimize compliance testing. the high integration level and the final test of each device before shipment also improve the overall quality, as the integrated discretes' components reduce the number of individual components, solder joints and pick and places processes.
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 35 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 7. abbreviations 8. references [1] sd specifications, part 1, physical layer specification version 2.00, may 9, 2006 [2] multi media card system specificatio n version 4.3, jesd84-a43, november 2007 [3] nxp semiconductor data sheet ip4853cx24_2 [4] nxp semiconductor data sheet ip4852cx25/lf [5] nxp semiconductor data sheet ip4052cx20/lf [6] nxp semiconductor data sheet ip4251_52_53_54_3 [7] nxp semiconductor data sheet ip4060cx16lf_1 [8] nxp semiconductor data sheet ip4051cx11/lf [9] nxp semiconductor data sheet ip4350cx24_1 [10] nxp semiconductor data sheet ip4352cx24_1 table 19. abbreviations acronym description cd card detect cdm command csp chip scale package dfn dual flat no-lead emi electromagnet ic interference esd electrostatic discharge hbm human body model iec international electrotechnical commission ldo low dropout mmc multi media card pcb printed-circuit board rf radio frequencies sd secure digital sdio secure digital input output spi serial peripheral interface wlcsp wafer level chip scale package wp write-protect
an10911_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 29 april 2010 36 of 37 nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning 9. legal information 9.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 9.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 9.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners.
nxp semiconductors an10911 sd(hc)-memory card and mmc interface conditioning ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 29 april 2010 document identifier: an10911_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 10. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 sd-memory card electrical interface . . . . . . . . 4 2.1 bus operation conditions . . . . . . . . . . . . . . . . . 4 2.2 sd-memory card bus timing conditions . . . . . . 6 2.3 capacitive load at t he interface conditioning device output . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 sd-memory card detect mechanism . . . . . . . . 9 3 mmc electrical interface . . . . . . . . . . . . . . . . . . 9 3.1 bus operating conditions . . . . . . . . . . . . . . . . . 9 3.2 bus timing conditions . . . . . . . . . . . . . . . . . . . 11 3.3 capacitive load at t he interface conditioning device output . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 sd-memory card and mmc interface comparison 12 5 passive esd protection and emi filter devices. . 12 5.1 esd protection emi filter devices in plastic package ip4252cz8-4, ip4252cz12-6, ip4252cz16-8 . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 application details of ip4252cz12-6 and ip4252cz16-8 . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 esd protection emi filter devices csp ip4051cx11/lf, ip4351cx11/lf . . . . . . . . . . 19 5.2.1 application information of ip4051cx11/lf and ip4351cx11/lf in an spi mode sd-memory card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 mmc esd protection and emi filter device ip4060cx16/lf . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.1 mmc interfacing using ip4060cx16/lf . . . . . 22 5.4 memory card interface using ip4052cx20/lf 22 5.4.1 sd-memory card interfacing using ip4052cx20/lf . . . . . . . . . . . . . . . . . . . . . . . 23 5.5 very highly integrated memory card interface devices ip4352cx24/lf and ip4350cx24/lf 25 5.6 active memory card voltage translator circuit ip4852cx25/lf . . . . . . . . . . . . . . . . . . . . . . . 28 5.7 active memory card voltage translator, power supply, esd protection and emi filter device ip4853cx24/lf . . . . . . . . . . . . . . . . . . . . . . . 31 6 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 legal information. . . . . . . . . . . . . . . . . . . . . . . 36 9.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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